AMD Interview Questions and Answers (2026)

A mod-3 counter on the rising edge gives a divide-by-3 output with a 33% duty cycle. To get 50%, generate one signal that is high for one and a half cycles using both edges: build the mod-3 counter on the rising edge, create a signal A that is high when the count is 0, create a copy B of A clocked on the falling edge, and OR them. A and B overlap by half a cycle, so the result is high for 1.5 of every 3 input cycles. Mention that mixing clock edges complicates timing analysis and that many teams prefer a PLL or a clock generator block for production designs.

Setup time is how long data must be stable before the capturing clock edge; hold time is how long it must stay stable after. A setup violation means the path is too slow for the clock period, fixed by reducing logic depth, pipelining or lowering frequency. A hold violation means data changes too soon after the edge, usually from a short path or clock skew, fixed by adding delay on the data path; frequency does not help. Either violation can put the flip-flop into a metastable state where the output settles unpredictably, which is why signals crossing clock domains go through two-flop synchronizers.

A sequence generates transaction objects; the sequencer arbitrates sequences and hands items to the driver through the seq_item_port; the driver converts transactions into pin-level activity on the virtual interface. A monitor watches the interface passively and broadcasts observed transactions through an analysis port to a scoreboard, which compares them against a reference model, and to coverage collectors. Driver, sequencer and monitor are grouped into an agent, which can be active or passive. The environment holds agents and scoreboards, and the test configures the environment through the config database and starts sequences. Expect follow-ups on phases (build, connect, run) and on objections that keep the run phase alive.

Split request and response handling into two parallel threads. The request thread gets items from the sequencer, drives the address phase, tags each item with an ID, stores it in an associative array keyed by ID, and moves on without waiting for the response, up to the allowed outstanding limit. The response thread watches the response channel, looks up the matching item by ID, fills in the response data and calls item_done or puts the response back to the sequence. Handle out-of-order responses if the protocol allows them, and add a timeout check for requests that never complete. This is the shape of the APB outstanding-transaction question reported from Bengaluru, though plain APB itself allows only one transfer at a time, so clarify the protocol variant first.

Caches are direct-mapped (each address maps to one line), fully associative (any line) or set-associative (one set of N lines). An address splits into tag, index and offset: the index selects the set, the tags in that set are compared in parallel, and on a hit the offset selects bytes within the line. On a miss the line is fetched and a victim is chosen by a policy such as LRU. Write-back caches mark lines dirty and write them on eviction; write-through caches write to the next level immediately. A 2025 Hyderabad candidate who joined as a fresher reported cache types and cache operation questions.

A virtual function is resolved at run time based on the object’s dynamic type. Compilers implement this with a vtable per class holding function pointers, and a hidden vptr in each object pointing to its class’s vtable; a virtual call loads the vptr, indexes the table and calls through the pointer. Destructors in a base class meant for polymorphic use must be virtual, or deleting through a base pointer skips the derived destructor. Pure virtual functions make a class abstract. Expect follow-ups on object size with a vptr, calling virtual functions in constructors, and the cost of virtual calls in hot loops.

Keep a write index starting at 0. Scan the array; for each non-zero element, write it at the write index and increment it. After the scan, fill the rest of the array from the write index with zeros. This is O(n) time and O(1) extra space. A swap-based version swaps each non-zero element with the position at the write index, which avoids the second pass and minimizes writes when there are few zeros. The 2025 Santa Clara intern was asked to run the optimized version, so test it on all zeros, no zeros and a single element.

A screening call, then two to four technical interviews, usually virtual on Microsoft Teams, then a manager or HR round. Hardware candidates are tested on digital design, computer architecture, Verilog and SystemVerilog and UVM; software candidates on C++, data structures, operating systems and debugging. Some India roles and campus drives start with an online test.

Digital design, bus protocols and UVM in a 2025 US report; testbench architecture, test planning and writing an APB outstanding-transaction driver function in UVM in an October 2023 Bengaluru report; and computer architecture, Verilog and SystemVerilog, digital design and Python, C or C++ in a 2024 Bengaluru phone screen.

C++ fundamentals and advanced C++, data structures such as linked lists and stacks, code debugging, and a puzzle, according to a May 2025 Software Engineer II candidate with four Teams rounds. A 2025 Santa Clara intern was asked Move Zeroes and Group Anagrams and had to run optimized code, and a 2025 Austin intern debugged assembly code.

For some roles, mostly in India. A September 2025 Bengaluru software engineer OA had MCQs on operating systems and C++ object-oriented programming plus two coding problems, one easy dynamic programming and one segment tree. A June 2025 Hyderabad intern had a test before the technical and HR rounds. Most US reports start with a call instead.

AMD’s US postings list base ranges. In 2026, a Santa Clara Design Verification Engineer posting listed $119,000-$170,000, a CPU Design Verification Engineer in Santa Clara $124,040-$177,200, a Software Development Engineer in Santa Clara $127,400-$182,000, and a Linux Kernel Software Engineer in Austin $101,500-$145,000. 2027 undergraduate software intern postings listed $60,320-$80,080 a year annualized depending on location.

Yes, mainly in Bengaluru and Hyderabad. AMD’s careers site lists hardware roles there such as CPU Design Verification Engineer in Bangalore and RTL Design Engineer, FPGA Prototyping Engineer and SoC Validation Engineer in Hyderabad, along with software roles. India postings do not show pay ranges.

Usually an online test for freshers and campus candidates, two technical rounds of about an hour each, and an HR round. An August 2025 Hyderabad hardware engineer had two technical rounds totaling about 1.5 hours on digital design, computer architecture and clock divider and multiplier circuits, and received an offer.

AMD’s careers page lists five key behaviors: Push the Limits, Drive Excellence, Be Direct and Humble, Collaborate Deeply, and Be Inclusive, Always. AMD job postings describe the culture as striving for execution excellence while being direct, humble, collaborative and inclusive.

It varies by team. An October 2023 Bengaluru design verification hire went from application to offer in about a week, while a 2025 Austin intern described a disjointed process with unusual follow-up times because individual teams, not HR, set the pace.

AMD’s design verification postings list Verilog, SystemVerilog and UVM, C and C++, and scripting in Python, Perl or TCL. An Austin methodology posting adds formal verification, make flows, Ruby and shell scripting, and a Bangalore posting adds assembly tests and JTAG debugging.