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Synopsys is an EDA (electronic design automation) company, so its India hiring splits between software-heavy R&D Engineer roles (DSA, C/C++, OS/DBMS) and VLSI-focused Application Engineer roles (digital electronics, CMOS, tool usage) across a 4-5 stage process.
Interview experience
Synopsys interview experiences covering Online Assessment, Technical Interview 1, Technical Interview 2, Technical Interview 3 (some roles), +1 more. Round-wise notes, common questions, and what candidates report clears each stage.
HR interview questions
Synopsys HR interview questions with sample answer frameworks - motivation, relocation, STAR stories, and culture-fit prompts.
| Round | Duration | What they test |
|---|---|---|
| Online Assessment | 60-90 min | Aptitude, coding, digital electronics (CMOS, K-maps, flip-flops) |
| Technical Interview 1 | 45-60 min | DSA (medium), C/C++, projects |
| Technical Interview 2 | 45-60 min | OOPs, OS, DBMS, Linux basics, more DSA |
| Technical Interview 3 (some roles) | 45-60 min | SystemVerilog/UVM/AXI for verification roles, or deeper digital-design depth |
| HR / Managerial Interview | 20-30 min | Motivation, fit, relocation, occasional puzzles |
These answers are compiled from public candidate reports and prep guides, not from an official Synopsys notice, and drives differ by campus and role. The instruction screen of your own test is the final word.
| Question | Answer |
|---|---|
| How many questions and how long? | Reports vary. A Bangalore R&D Engineer report describes 36 MCQs in 1 hour worth 1-3 marks each; an R&D FTE report describes 20 CS, 15 aptitude and 8 electronics MCQs in untimed sections; another on-campus report describes 60 MCQs across quant, logic, C, C++, DSA and digital design. |
| Does it have negative marking? | Reports conflict. The Bangalore R&D Engineer report says a wrong answer cost 50% of that question’s marks; the R&D FTE report says there was no negative marking. Read the instructions before you guess. |
| Is there a sectional cutoff? | Not published, and no candidate report we read describes one. Shortlists are small: in one drive 14 of about 100 candidates cleared the test. |
| What is the eligibility cutoff? | Not one fixed number. GfG’s Synopsys recruitment page cites 75%+ in B.Tech, 10th and 12th with no backlogs at the time of interview; one Noida drive reportedly set 8.5 CGPA. 7.5 CGPA or 75% is the floor most often quoted. |
| Which platform is it on? | No campus report names one, and some drives run the test offline on paper. |
| Is there coding in the test? | Usually not. The test is mostly MCQs on C output, aptitude and digital electronics; one Noida drive added a subjective coding question. Live coding comes in the interviews. |
| How many interview rounds follow? | Often more than at other chip companies. GfG’s recruitment page lists anywhere from 5 to 8 rounds including the test, and one R&D FTE candidate had four face-to-face technical rounds. |
The technical rounds follow the role. These are questions candidates have reported on GeeksforGeeks and Glassdoor; they show the level and style, not a fixed list.
| Track | Reported questions and topics |
|---|---|
| R&D engineer (software) | Stages of compilation. Static vs shared libraries and the library load path. Loader vs linker. int *p[10] vs int (*p)[10]. Allocate a 2D array with malloc and with new. Find the 0-to-1 transition in an infinite sorted binary array in O(log n). XOR from NAND gates. |
| R&D engineer (software, later rounds) | Reverse a linked list. Implement your own vector class. Name mangling. Check whether a graph is bipartite and validate a BST. Design an elevator system with full code. Pipelining and cache coherence. |
| Design / verification / application engineering | Latch vs flip-flop. Setup and hold with examples. Priority encoder RTL with if-else vs case. Verilog for a mux, a counter and an asynchronous reset. Full adder from a K-map. FSM for an overlapping “1010” detector. STA from basics to numericals. |
Asked across every track: your projects and internships, puzzles such as timing 45 minutes with two burning wires and the mislabelled jars, and “Why Synopsys?”. Application Engineer postings in India usually ask for experience, so most freshers enter as R&D engineers or through design and verification campus drives.
An aptitude and coding screen with a digital-electronics section layered in - CMOS, K-maps, and flip-flops carry more weight for VLSI-adjacent applicants than for pure software req’s. Candidate reports describe ~60–90 minute tests: some drives use untimed sections (CS MCQs, aptitude, electronics); intern loops mention 90-minute three-part software + digital papers on HirePro-style platforms. Explain your reasoning out loud in later rounds - silent coding without commentary is a commonly reported rejection signal.
Common questions
Expect medium-difficulty DSA (dynamic programming, binary trees, shortest paths/MST, BFS/DFS applications), C/C++ and OOPs fundamentals, OS and DBMS basics, and Linux commands if listed on your resume. Later rounds often go deep on any ML/deep-learning project.
Common questions
Application Engineer and VLSI-focused req’s shift the technical bar toward digital electronics, CMOS, and chip-design-flow understanding rather than DSA. Verification-specific loops add SystemVerilog, UVM, and protocol questions.
Common questions
Round-by-round breakdowns are on the Synopsys interview experience page.
A closing round on motivation, academics, and fit - candidate reports mention this sometimes doubling as a managerial conversation, and occasionally including a lateral-thinking puzzle alongside the usual questions.
Common questions
Sample answer frameworks for each of these are on the Synopsys HR interview questions page.
Like other EDA companies, Synopsys builds the software tools chip designers use and separately staffs application engineers who work directly with those tools and customers. R&D Engineer req’s are evaluated on DSA, C/C++, and CS fundamentals; Application Engineer req’s are evaluated on digital electronics, CMOS, and VLSI-tool literacy instead. Confirm your track before assuming your prep should be DSA-heavy.
Total power is dynamic plus short-circuit plus static leakage. Dynamic switching power is alpha times C times V squared times f, where alpha is the activity factor - it dominates in active operation, which is why supply-voltage scaling buys quadratic savings and clock gating cuts alpha. Short-circuit power flows during the brief window when both the pull-up and pull-down networks conduct as the input crosses the threshold, and it is minimised by keeping input transition times fast. Static power comes from subthreshold conduction, gate-oxide tunnelling, and junction leakage, and it grows sharply as the threshold voltage shrinks at advanced nodes, which is why power gating and multi-Vt cell libraries exist.
Setup time is how long the data input must be stable before the active clock edge, and hold time is how long it must remain stable after that edge. A setup violation means the data path is too slow relative to the clock period, so it is fixed by shortening the combinational path, upsizing cells, or lowering the frequency. A hold violation means the data path is too fast, so it is fixed by inserting buffers or delay cells in the data path - lowering the frequency does not help, which is the point interviewers check. Violating either can drive the flip-flop metastable, where the output settles to an unpredictable value after an unbounded delay, which is why crossing clock domains needs a two-flop synchroniser.
Plot the minterms on a Karnaugh map whose rows and columns follow Gray-code ordering, so physically adjacent cells differ in exactly one variable. Group ones into rectangular blocks of size a power of two, making each group as large as possible and allowing overlaps, then read off one product term per group by keeping only the variables that stay constant inside it. Wrap-around across edges and corners is legal because the map is toroidal. Don’t-care cells, arising from input combinations that cannot occur, may be included in a group whenever doing so makes it larger, which yields a cheaper implementation without changing behaviour on any real input.
Dijkstra finds single-source shortest paths in a graph with non-negative edge weights, running in O((V + E) log V) with a binary heap, because it finalises the closest unfinalised vertex at every step - a negative edge would invalidate that greedy choice. Bellman-Ford handles negative weights, runs in O(V times E) by relaxing every edge V minus one times, and detects a negative cycle if any edge still relaxes on an extra pass. Use Dijkstra for road networks and routing metrics; use Bellman-Ford when edges can be negative, as in currency arbitrage or distance-vector routing. For all-pairs on a dense graph, Floyd-Warshall at O(V cubed) is simpler than running either one V times.
Sort all edges by weight ascending, then take each edge in turn and add it to the tree only if its two endpoints are in different components, which you test with a disjoint-set union structure. Stop once you have V minus one edges. With path compression and union by rank the find and union operations cost near-constant amortised time, so the total is O(E log E) dominated by the sort. Prim’s algorithm is the alternative and is preferable on dense graphs, where a heap-based Prim runs in O(E + V log V); Kruskal suits sparse graphs and edge lists. Both are correct because of the cut property - the lightest edge crossing any cut belongs to some MST.
Define dp[i][w] as the best value using the first i items with capacity w. For each item you either skip it, giving dp[i-1][w], or take it when its weight fits, giving value[i] plus dp[i-1][w - weight[i]], and you keep the maximum. The answer is dp[n][W], with time O(n times W) and space O(n times W), reducible to O(W) by iterating the weight loop downward over a single row so each item is used at most once. That downward iteration is exactly what separates 0/1 knapsack from the unbounded variant, where you iterate upward. Note the complexity is pseudo-polynomial, since W is a value rather than an input length, so a huge capacity makes the DP impractical.
Start with top or htop sorted by resident set size, or ps aux with a sort on RSS, to identify the process id. Then read /proc/PID/status and /proc/PID/smaps for a breakdown between anonymous memory, file-backed mappings, and shared pages, since RSS double-counts shared libraries. Use pmap -x PID to see which mappings are growing, strace -p PID to watch mmap and brk calls, and lsof -p PID for leaked file descriptors. free -m plus vmstat 1 shows whether the system is swapping, and dmesg reveals whether the OOM killer has already intervened. Naming /proc rather than only top is what usually distinguishes a strong answer here.
In SystemVerilog, logic is a four-state type that replaces both reg and wire for single-driver signals, and it can be assigned in both procedural blocks and continuous assignments - the old Verilog rule that reg means storage was always a misnomer, since reg only meant procedurally assigned. Use wire only where you genuinely need multiple drivers or a resolved net. In UVM, the standard testbench has a sequencer generating sequence items, a driver converting them into pin-level activity, a monitor observing the interface passively, an agent bundling those three, a scoreboard checking actual against expected, and a coverage collector. The environment holds the agents and the test configures and starts the sequences, with the factory and config_db enabling override without editing testbench code.
Classes with virtual methods get a hidden vptr per object pointing at a vtable of function pointers. Calls through a base pointer index the vtable at runtime - dynamic dispatch. Adding virtual functions increases object size by one pointer; constructors run vptr setup. Synopsys R&D panels often ask keyword-placement variants in sample code - read declarations carefully.
Both allocate on the heap. malloc takes bytes and leaves contents uninitialized; calloc takes count × size and zero-initializes. free releases either. Interviewers follow with stack vs heap, fragmentation, and why C++ prefers new/delete with constructors. Mention checking return values and avoiding double-free.
Walk with three pointers (prev, curr, next), reverse curr->next each step, return prev at the end. O(n) time, O(1) space. Recursive version uses O(n) stack space. Campus reports expect clean base cases and verbal test cases - palindrome-linked-list variants appear in intern loops.
BFS or DFS coloring with two colors; if an edge connects same-colored nodes, the graph is not bipartite. Equivalent to detecting odd-length cycles. Reported in Synopsys R&D FTE drives alongside standard shortest-path prep.
When deleting through a base pointer, a virtual destructor ensures derived destructors run - otherwise derived members leak. Rule of thumb: if any method is virtual, destructor should be virtual. Tied to RAII and smart-pointer usage in modern C++ interviews.
Preprocessor → compile to object files → link (resolve symbols, merge static/shared libs) → loader maps executable into memory. Set 6-style Synopsys reports ask linker vs loader, static vs shared libraries, and PATH - connect to debugging undefined references.
Reports conflict. A Bangalore R&D Engineer report says a wrong answer cost 50% of that question’s marks, while an R&D FTE report says there was no negative marking, so read the instructions of your own test before guessing.
Synopsys does not publish a test cutoff. Eligibility is usually 7.5 CGPA or 75% with no backlogs, though one Noida drive reportedly set 8.5 CGPA, and the test itself is mostly MCQs on aptitude, C output and digital electronics rather than coding.
Synopsys campus hiring for R&D Engineer roles typically runs an Online Assessment followed by three Technical Interviews and a closing HR round. The Online Assessment (60-90 minutes) covers aptitude, coding, and digital electronics/CMOS basics. Technical interviews (45-60 minutes each) go deep on DSA (medium-level problems including dynamic programming and trees), C/C++, OS, DBMS, and often digital logic design, with later rounds adding project deep-dives, OOPs, and sometimes ML/deep-learning discussion if it’s on your resume. Application Engineer roles - a separate track - lean more on VLSI/tool-usage fundamentals than DSA.
Synopsys interviews mix DSA/coding problems (arrays, trees, graphs, shortest-path/MST, sorting) with core CS fundamentals - OS, DBMS, OOPs, Linux commands - plus digital electronics topics such as flip-flops, K-maps, and CMOS power dissipation. Verification-focused profiles get SystemVerilog, UVM, and AXI protocol questions. Candidates report deep dives into any ML/deep-learning project on their resume, plus occasional puzzles (like the classic 3-and-5-litre jug problem) in managerial rounds.
For R&D Engineer roles, Synopsys typically runs an Online Assessment plus three Technical Interviews and a closing HR/managerial round. EDA/VLSI-focused and Application Engineer roles sometimes swap one technical round for deeper digital design or verification depth instead of DSA.
Both. Synopsys is an EDA company - it builds chip-design software, so its R&D Engineer roles (DSA, C/C++, OS/DBMS, sometimes digital logic) are software-heavy, while its Application Engineer roles work directly with VLSI tools and customers and lean more on digital electronics, CMOS, and chip-design-flow fundamentals than on DSA. Check your req title before you decide how to prep.
For R&D Engineer roles, practise medium-level DSA (dynamic programming, trees, graphs), and revise OS, DBMS, and OOPs fundamentals along with basic Linux commands. For Application Engineer/VLSI-track roles, prioritise digital electronics fundamentals (CMOS, K-maps, flip-flops) instead. Verification candidates should brush up on SystemVerilog and UVM. Prepare one clear project narrative - ML/deep-learning projects get probed in real depth - and use STAR for HR answers.
EDA / semiconductor software and hardware-adjacent roles filter on CS plus domain. Interviewers score:
Soft fail modes: pure web-dev stories for an EDA tools role, or claiming tool expertise you cannot whiteboard.
Campus R&D loops commonly mix C/C++ depth (pointers, virtual functions, memory) with DSA on lists/trees/graphs and, for some tracks, digital or OS questions. Be ready to implement structures carefully (including your own vector-like container in some reports) and to discuss projects with cache/pipelining vocabulary when relevant - not a pure web-SDE narrative.
Use this as a default four-week loop before a Synopsys drive. Adjust to your invite timeline.
10-day crash version: Days 1-4 timed DSA, days 5-7 resume projects + CS fundamentals, days 8-9 mock interviews out loud, day 10 HR STAR stories on the HR page.
Candidate-reported fresher/early-career packages for Synopsys often cite ₹16-30 LPA reported band. Treat forum numbers as ranges, not guarantees - confirm the written offer letter for your team and location.
Interview process details and sample questions on this site are editorially organized from public candidate reports and hiring write-ups, with round structure, prep notes, and company-specific framing added by our team. For round-by-round stories, see the Synopsys interview experience page. For OA papers and coding drills, use Synopsys on placementpapers.app. OA quick answers and track-wise questions draw on GeeksforGeeks interview experiences for Synopsys R&D Engineer campus and FTE roles, GfG’s Synopsys recruitment-process page and Glassdoor candidate reviews.
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