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Interview Questions

ISRO Interview Experience 2026

Overview

ISRO Scientist/Engineer ‘SC’ hiring is not campus placement - it runs through the ISRO Centralised Recruitment Board (ICRB) with timelines published on isro.gov.in. The process map is shortlisting (GATE score or ICRB written, depending on the notification) → document verification → a single high-stakes personal interview (often 25–40 minutes, large panel, whiteboard). Motivation and relocation questions usually appear inside that same sitting, not as a separate 30-minute HR round.

Patterns shift by discipline and year: CS/ECE/Mechanical often shortlist on GATE score; other posts still use an ICRB written. Merit is commonly quoted as 50% shortlist + 50% interview, so the panel can flip the offer. Practise whiteboard derivations from favourites and from random core topics the panel may hop to.

Eligibility (notification-style): typically 65% aggregate / CGPA 6.84/10 in the qualifying degree in the advertised discipline; age and category relaxations per advertisement.

Fresher compensation (candidate-reported): Level 10 (~₹8–12 LPA all-in in forum notes) - confirm on the appointment letter.

How ISRO differs from campus product companies

  • No multi-round DSA loop. Standard Scientist/Engineer ‘SC’ reports describe one panel interview after score-based shortlisting.
  • Interview weight is real. Unlike many PSUs where the interview is confirmatory, ISRO quotes roughly half the merit on the panel.
  • Panel size and whiteboard matter. Reports cite 6–13 scientists present; you will be sent to the board.
  • Favourites are not a safe harbour. Panels ask preferences, then often hop to Security, Software Engineering, or other core areas.

Round-wise process

Round Duration What they test
GATE score or ICRB written test ~90 min, ~80 Qs Discipline-specific technical (no aptitude section)
Technical Interview ~25-45 min Core subjects + project defence, before a large panel
Document verification - Certificates, category, eligibility (usually the day before the interview)

Real interview experiences

ISRO is not campus hiring, so there is no “OA → 3 rounds → HR” story to tell. Scientist/Engineer ‘SC’ recruitment runs through the ISRO Centralised Recruitment Board (ICRB), and the whole thing comes down to one shortlisting score plus one panel interview. Public write-ups are correspondingly thin - a single 25-minute interview does not generate much to report. Here is what recurs.

How selection actually works

  • The shortlist is score-driven, not resume-driven. In recent ICRB cycles the Computer Science, Electronics and Mechanical disciplines are shortlisted on GATE score (the score, not the marks or the AIR), commonly quoted at a 1:7 ratio against vacancies. Other disciplines and other post types still use an ICRB written test - objective, discipline-specific, around 80 questions in 90 minutes with negative marking - and shortlist at roughly 1:5, subject to a floor on total candidates.
  • The interview carries half the weight. Reported and notification-quoted merit is 50% written/GATE + 50% interview, with a minimum of 50% in each stage and a 60% aggregate for unreserved candidates (relaxed for reserved categories). Unlike PSUs where the interview is confirmatory, at ISRO you can genuinely lose or win here.
  • Document verification happens the day before, and the interview the next day - candidates report being called to a centre for both.
  • Always read that cycle’s official ICRB advertisement. Weightage, shortlisting basis and eligibility have changed between notifications.

Experience 1: Scientist/Engineer ‘SC’, Computer Science (Bengaluru, 2024)

  • Panel size is the thing people are unprepared for. This account reports a panel of 10 members on paper, 6 present on the day. Other CS write-ups describe 7-8 senior scientists. There is a whiteboard in the room and you will be sent to it.
  • Duration ~25 minutes. Around 30 candidates were interviewed that day across morning and afternoon slots.
  • Subjects covered: Operating Systems, DBMS, Computer Networks, and Security, which was pushed hardest in this account. Plus a defence of the B.Tech project.
  • The panel did not stay inside the candidate’s stated favourite subjects. The write-up’s own takeaway is that questions came from random areas of core CS - so a two-subject prep strategy is risky here even though you are asked to name preferences.
  • Expect derivations and problem-solving on the board, not verbal-only answers.

Takeaways

  • What decided it: Surviving a large panel with board work across OS, DBMS, networks, and security, plus an honest project defence
  • Common fail: Naming favourites then folding when the panel hops to other core CS topics
  • How to practise: Whiteboard drills on random core topics; prepare security and project “why algorithm X not Y” answers

Experience 2: Scientist ‘SC’, Computer Science (panel favourites + Software Engineering)

Takeaways

  • What decided it: Depth on listed favourites (why / how / advantages / applications) plus SE concepts even when SE was not named
  • Common fail: Memorising definitions without applications, or omitting SE entirely from prep
  • How to practise: List 4–5 favourites including SE; rehearse each concept with one real application and one trade-off

Experience 3: Scientists ‘C’ (VLSI), SAC Ahmedabad

  • Source: GeeksforGeeks - Scientists ‘C’ VLSI interview.
  • Panel: ~12–13 members; chairman-led; ~25 minutes.
  • Topics: M.Tech VLSI project and design flow; low-power techniques; 180 nm vs 5 nm comparison; op-amp classes, CMRR, positive feedback uses.
  • Tip: Senior-grade post, but the depth and whiteboard style mirror what ‘SC’ candidates report - expect comparative technology questions, not trivia.

Takeaways

  • What decided it: Comparative tech answers (process nodes, design flow) on the board, not buzzwords
  • Common fail: Reciting VLSI jargon without comparing trade-offs
  • How to practise: One comparison table per major topic (power, nodes, amp classes)

Experience 4: Scientist/Engineer ‘SC’, Electronics & Communication (Delhi panel)

  • Source pattern: ECE interview question lists from selected-candidate forums (linked under Sources).
  • Setting: U-shaped table, whiteboard mandatory; ~25–30 minutes (panels can run 30–40).
  • Reported question themes: Convert sine → square → sine on the board; BPF cascades and bandwidth; Q-factor; solar-cell efficiency; waveguide cutoff; logic families and ADC types; RAM refresh; Helmholtz equation in 3-D.
  • Tip: ECE interviews skew circuits + EM + materials; analog/digital breadth beats picking only two favourites.

Takeaways

  • What decided it: Board derivations across circuits, EM, and devices under time pressure
  • Common fail: Narrow favourite list that leaves EM or materials blank
  • How to practise: Timed whiteboard sketches: sine→square conversion, BPF cascade, waveguide cutoff

Experience 5: Written exam + interview (ICRB mode)

  • Source pattern: ICRB written + interview prep write-ups (linked under Sources).
  • Written: 80 questions, high negative marking - accuracy over guessing.
  • Interview: 7–8 scientists, 20–40 minutes; do not bluff; whiteboard use encouraged.
  • Outcome lens: Merit often quoted as 50% written/GATE + 50% interview with category-wise minimums - check your cycle’s notification.

Takeaways

  • What decided it: Accuracy on negative-marked written plus honest, board-first interview answers
  • Common fail: Guessing through the written; bluffing in the panel
  • How to practise: Timed accuracy drills; “I don’t know, here is how I would reason” scripts

What other candidate accounts add

  • Interviews commonly open with the final-year or current job project on the board - that sets the tone.
  • Random syllabus hops happen even after you name favourites (Bengaluru CS reports linked under Sources).
  • There is no LeetCode coding round for standard Scientist ‘SC’ reports - fundamentals beat competitive-programming volume.

Pre-interview checklist (ISRO Scientist/Engineer ‘SC’)

  • Read this cycle’s ICRB advertisement for shortlist basis (GATE vs written), weightage, and eligibility
  • Prepare 4–5 favourite subjects with why/how/applications depth; add Software Engineering for CS
  • Rehearse final-year project on a whiteboard (algorithm choice, alternatives, failure modes)
  • Practise negative-marked accuracy if your cycle uses an ICRB written
  • Motivation pack for the same panel: Why ISRO, centre preference, bond/relocation honesty
  • Document folder ready the day before; expect a large panel and a short slot

Questions that come up often

Coding / technical

  1. Basic C output and pointers. Usually expects language fundamentals
  2. Stack vs queue use-cases. Usually expects DSA basics
  3. Core-subject numericals from your branch. Usually expects domain depth
  4. Discussion on core technical and electronics/CS fundamentals, bottlenecks, failure modes, simple APIs
  5. Detailed project discussion, architecture, hardest bug, what you would change

HR / behavioural

  1. Why this organisation / PSU?
  2. Bond acceptance
  3. Preferred posting
  4. Willingness to relocate

Practical tips for ISRO

  • Clear the screening round first. Timed practice beats last-minute topic hopping.
  • For domain questions, explain core technical in plain language, inputs, outputs, what breaks at scale.
  • OOPs and SQL still open a lot of ISRO panels. Do not skip fundamentals.
  • HR answers should be concrete. One story with a result beats five slogans.
  • If you do not know something, say so and outline how you would find out.

HR and motivation (same panel)

Expect Why ISRO?, centre preference, bond/service rules, and relocation in the same room as thermodynamics or OS questions. Prepare framed answers on the HR interview questions page rather than treating motivation as an afterthought.

Sample answers for high-frequency questions

Use these as frames, not scripts - interviewers probe follow-ups.

Q. What does negative feedback do to a control system, and how do you check stability?
A. Negative feedback subtracts a measured output from the reference input, so the controller acts on the error. That reduces sensitivity to plant parameter variation and disturbances, widens bandwidth and improves linearity, at the cost of reduced overall gain and a risk of instability if the loop phase shift approaches 180 degrees while the loop gain is still above unity. For a linear time-invariant system, stability means every closed-loop pole lies in the left half of the s-plane. You test this without factoring the characteristic polynomial using the Routh-Hurwitz criterion - the number of sign changes in the first column of the Routh array equals the number of right-half-plane poles - or graphically with gain and phase margins on a Bode plot.

Q. State the sampling theorem and explain aliasing.
A. The Nyquist-Shannon sampling theorem says a signal band-limited to a maximum frequency fm can be reconstructed exactly from samples taken at a rate greater than 2fm; that threshold, 2fm, is the Nyquist rate. If you sample slower, frequency components above half the sampling rate fold back and appear as lower frequencies that are indistinguishable from genuine ones - that is aliasing, and no processing afterwards can undo it. The fix is an analogue anti-aliasing low-pass filter before the ADC, which is why every real telemetry or imaging chain places the filter ahead of the sampler rather than after it.

Q. What are setup time and hold time in a digital circuit?
A. Setup time is the interval before the active clock edge during which the data input must already be stable; hold time is the interval after the edge during which it must stay stable. Violate either and the flip-flop can go metastable, settling to an unpredictable value after an unbounded delay. A setup violation means the data path is too slow, so you fix it by shortening combinational logic, pipelining, or lowering the clock frequency. A hold violation means the path is too fast and is independent of clock period, so you fix it by adding buffer delay in the data path. Crossing clock domains needs a synchroniser, typically two cascaded flip-flops.

Q. State the first and second laws of thermodynamics and explain Carnot efficiency.
A. The first law is conservation of energy for a system: the heat added equals the change in internal energy plus the work done, or dQ = dU + dW. It says energy cannot be created or destroyed but places no limit on direction. The second law supplies that direction - entropy of an isolated system never decreases, and no engine can convert heat entirely into work while operating in a cycle. The Carnot cycle sets the upper bound on efficiency between two reservoirs: efficiency = 1 minus T_cold divided by T_hot, with temperatures in kelvin. So an engine between 800 K and 300 K cannot exceed 62.5 percent, no matter how it is built - a real engine is always lower because of irreversibilities.

Q. What is the difference between stress and strain, and what does the stress-strain curve tell you?
A. Stress is internal force per unit area (N/m squared, or pascal); strain is the resulting fractional deformation, change in length over original length, and is dimensionless. In the initial linear region they follow Hooke’s law, stress = E times strain, where E is Young’s modulus - the slope, a measure of stiffness. The curve then passes the proportional limit and yield point, after which deformation is plastic and permanent, rises to the ultimate tensile strength, and ends at fracture. A ductile material like mild steel shows a long plastic region and necking before failure, while a brittle material like cast iron fractures with almost no plastic warning - which is why launch-vehicle structures are designed with yield and ultimate factors of safety against limit loads.

Tips from successful candidates

Assessment tips

  • Confirm the current ISRO pattern from the drive mail before practising old papers
  • Finish one problem or section fully before starting the next
  • Revise the fundamentals listed in the round table on this page

Interview tips

  • Narrate trade-offs; expect “why” after every answer
  • Only list projects you can defend under follow-ups
  • Prepare 3-4 STAR stories for behavioural prompts

HR tips

  • Know why ISRO, not just why the industry
  • Be clear on location / notice period / higher studies
  • Practise answers on the dedicated HR page

Sources

These links are research inputs we used to map ICRB shortlisting, panel size, whiteboard style, and recurring subject themes - not copied page mirrors. We reorganized reports into a process table, takeaways, and a prep checklist for ISRO.

Always cross-check the official ICRB notification for that cycle; weightage and shortlist rules change.

For the company overview, see the ISRO hub. For motivation and relocation frames, use the ISRO HR page. For practice papers, see ISRO placement papers.

ISRO hub

HR interview questions

Placement papers

Preparation guide

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